1. Field of the Invention
The present invention relates to a reprogramming device of a flash memory. More particularly, the present invention relates to a reprogramming device of a flash memory which makes the damaged flash memory usable again by reprogramming the flash memory.
2. Description of the Related Art
As is well-known, an effective memory and an effective memory handling is neccessary for an effective computer system. Among memories of a computer system, some situations involving memories (such as those involving flash memories) may require operations such as reprogramming, refresh, etc. before being usable again. An exemplar, of a contemporary practice in the related arts, is Tsuha (U.S. Pat. No. 5,511,176, Microcomputer Capable Of Accessing To An External Memory With Least Possible Wait, Apr. 23, 1996) disclosing a microcomputer capable of accessing to an external memory with least possible wait. In a refresh pulse producing circuit of a microcomputer, an access detection section detects access to a non-refresh memory area of an external memory to produce a non-refresh memory signal indicative of the access. Cartman et al. (U.S. Pat. No. 5,479,640, Memory Access System Including A Memory Controller With Memory Redrive Circuitry, Dec. 26, 1995) discloses a memory access for improving memory access when addressing dynamic random access modules (DRAMs). The memory access system includes a main memory and a memory controller. The main memory hardware redrives the last row address to the DRAMs after the completion of an access, so that the memory controller need not provide a row address to the memory for each command of a command sequence. Wada (U.S. Pat. No. 5,475,645, Memory Module Using DRAM And Method Of Refreshing The Memory Module, Dec. 12, 1995) discloses a memory module using a large capacity DRAM without a self-refresh mode, which maintains the contents of the memory irrespective of non-input of a refresh signal from a computer. Vrba (U.S. Pat. No. 5,473,770, Fault-Tolerant Computer System With Hidden Local Memory Refresh, Dec. 5, 1995) discloses a fault tolerant computer system having a plurality of processor modules having independent clocks for processing an instruction stream, global memory accessible by all of the processor modules, and a local memory configured within each processor modules and clocked synchronously therewith. The local memory is periodically refreshed or the refresh is aborted depending upon the number of clock cycles available before a local memory access occurs. Garinger et al. (U.S. Pat. No. 5,465,339, Decoupled Refresh On Local And System Busses In A PC/AT Or Similar Microprocessor Environment, Nov. 7, 1995) disclose a decoupled refresh on local and system busses in a PC/AT or similar microprocessor environment. Sugimoto (U.S. Pat. No. 5,440,711, Method For Controlling DRAM Memory In A Microcomputer, Aug. 8, 1995) discloses a microcomputer capable of elimination of the need of an external circuit and hence timing adjustment of the same, and of direct connection thereof to a memory. The DRAM controller includes a refresh controller for refreshing a DRAM. My study of the prior art and of the contemporary practice indicates a need for an effective reprogramming device of a flash memory which makes the damaged flash memory usable again by reprogramming the flash memory.